Strained gate electrodes in semiconductor devices

ABSTRACT

Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.

TECHNICAL FIELD

This invention relates generally to semiconductor devices, and morespecifically to metal oxide semiconductor (MOS) devices having strainedchannel regions.

BACKGROUND

Miniaturization of metal-oxide-semiconductor field-effect transistors(MOSFETs) has improved speed performance and reduced cost per unitfunction of integrated circuits. One way to improve transistorperformance is through selective application of stress to the transistorchannel region. Stress distorts or strains the semiconductor crystallattice and interatomic bonding. The strain, in turn, affects the bandalignment and charge transport properties of the semiconductor. Bycontrolling the magnitude and distribution of stress in a finisheddevice, manufacturers can increase carrier mobility and improve deviceperformance. There are several existing approaches of introducing stressin the transistor channel region.

One approach includes forming an epitaxial, strained silicon layer on arelaxed silicon germanium (SiGe) layer. Because SiGe has a largerlattice constant than Si, the epitaxial Si grown on SiGe will have itslattice stretched in the lateral direction, so the Si will be underbiaxial tensile stress. In this approach, the relaxed SiGe buffer layeris referred to as a stressor that introduces stress in the channelregion. The stressor, in this case, is placed below the transistorchannel region. In another approach, a high-stress film is formed over acompleted transistor. The high-stress film distorts the silicon latticethereby straining the channel region.

One problem facing CMOS manufacturing is that NMOS and PMOS devicesrequire different types of stress in order to achieve increased carriermobility. For example, a biaxial, tensile stress increases NMOSperformance approximately twofold. However, for a PMOS device, such astress yields almost no improvement. With a PMOS device, a tensilestress improves performance when its perpendicular to the channel, butit has nearly the opposite effect when it is parallel to the channel.Therefore, when a biaxial, tensile film is applied to a PMOS device, thetwo stress effects almost cancel each other out.

Workers are aware of these problems. Therefore, new CMOS manufacturingtechniques selectively address PMOS and NMOS devices. An NMOSfabrication method includes using tensile films to improve carriermobility. A PMOS fabrication method includes using substrate structuresthat apply a compression stress to the channel. One PMOS method includesselective application of a SiGe layer into the source/drain regions.Another method uses modified shallow trench isolation (STI) structuresthat compress the PMOS channel.

The use of additional materials, however, adds further processing stepsand complexity to the manufacturing process. Therefore, there remains aneed for improving the carrier mobility of both NMOS and PMOS deviceswithout significantly adding to the cost or complexity of themanufacturing process.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved by preferred embodiments ofthe present invention that provide methods and structures forintroducing stress and strain into semiconductor devices in order toimprove charge carrier mobility.

Embodiments of the invention provide a semiconductor device and a methodof manufacture. A preferred embodiment of the invention includes forminga tensile strained channel region in an NMOS device and a compressivestrained channel region in a PMOS device.

One embodiment comprises forming an intermediate structure, wherein theintermediate structure comprises a first active region, a second activeregion, a first gate electrode layer over the first active region, and asecond gate electrode layer over the second active region. Embodimentsmay further comprise converting the first gate electrode layer to anamorphous portion and a polycrystalline portion, and forming a cappinglayer over the intermediate structure. The first and second gateelectrode layers are recrystallized so that an average crystal grainsize of the first recrystallized layer is less than an average crystalgrain size of the second recrystallized layer. The cap layer may beremoved after the recrystallizing. The first and second gate electrodelayers are patterned to form a first gate electrode over the firstactive region and a second gate electrode over the second active region,wherein the first and second gate electrodes have different intrinsicstresses.

Another embodiment of the invention provides a semiconductor structure.The structure comprises a first gate electrode over a first activeregion and a second gate electrode over a second active region.Preferably, the first gate electrode comprises one of an amorphous gateelectrode and a polycrystalline gate electrode. In another embodiment,the first gate electrode is an amorphous gate electrode, and the secondgate electrode is a polycrystalline gate electrode. In an embodiment,the first active region includes a tensile strained region under thefirst gate electrode. The second active region may include a compressivestrained region under the second gate electrode.

Another embodiment of the invention provides a semiconductor device. Thedevice comprises a first gate electrode over a first active region and asecond gate electrode over a second active region. The first gateelectrode comprises a first plurality of crystal grains having a firstaverage grain size, and the second gate electrode comprises a secondplurality of crystal grains having a second average grain size.Preferably, the first average grain size is less than the second averagegrain size.

In still another embodiment, the semiconductor device may comprise anNMOS device and a PMOS device, each device comprising a source/drainregion in a substrate, a channel region in the substrate between thesource/drain region, and a polycrystalline gate electrode over thechannel region. Preferably, an average crystal grain size of the NMOSpolycrystalline gate electrode is less than an average crystal grainsize of the PMOS polycrystalline gate electrode. The NMOSpolycrystalline gate electrode may be a material having an intrinsiccompressive stress that causes a tensile strain in the NMOS channelregion. The PMOS polycrystalline gate electrode may comprise a materialhaving an intrinsic tensile stress that causes a compressive strain inthe PMOS channel region.

In embodiments of the invention, the second recrystallized layercomprises a plurality of crystal grains having a columnar growthorientation, and the first recrystallized layer comprises a plurality ofcrystal grains having an equiaxed growth orientation. The firstrecrystallized layer may comprise a first portion on a second portion,wherein an average crystal grain size of the first portion is less thanan average crystal grain size of the second portion.

Embodiments may further include adding a stressor to the gate electrodestack. The embodiments include forming a first stressor having anintrinsic compressive stress under the first gate electrode, and forminga second stressor having an intrinsic tensile stress under the secondgate electrode.

Note that although the term layer is used throughout the specificationand in the claims, the resulting features formed using the layer shouldnot be interpreted as only a continuous or uninterrupted feature. Aswill be clear from reading the specification, the layer may be separatedinto distinct and isolated features (e.g., active regions or devicefabrication regions), some or all of which comprise portions of thesemiconductor layer.

Additional features and advantages of embodiments of the invention willbe described hereinafter, which form the subject of the claims of theinvention. It should be appreciated by those skilled in the art that thespecific embodiments disclosed might be readily utilized as a basis formodifying or designing other structures or processes for carrying outthe purposes of the present invention. It should also be realized bythose skilled in the art that such equivalent constructions andvariations on the example embodiments described do not depart from thespirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1 a and 1 b are cross-sectional views of a gate electrode layeraccording to embodiments of the invention;

FIGS. 2 a and 2 b are cross-sectional views of an amorphization implantaccording to embodiments of the invention;

FIGS. 3 a-3 d are cross-sectional views illustrating a capping layer andgate electrode layer recrystallization according to embodiments of theinvention;

FIGS. 4 a-4 b are cross-sectional views illustrating crystal grains ingate electrodes according to embodiments of the invention;

FIG. 5 is a cross-sectional view of a CMOS device according to theembodiments of the invention; and

FIGS. 6 a and 6 b are cross-sectional views illustrating additionalstressors incorporated within gate electrodes according to embodimentsof the invention

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the preferredembodiments and are not necessarily drawn to scale. To more clearlyillustrate certain embodiments, a letter indicating variations of thesame structure, material, or process step may follow a figure number.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention. Theintermediated stages of manufacturing a preferred embodiment of thepresent invention are illustrated throughout the various views andillustrative embodiments of the present invention.

This invention relates generally to semiconductor device fabrication andmore particularly to structures and methods for strained transistors.The present invention will now be described with respect to preferredembodiments in a specific context, namely the creation of PMOS and NMOStransistors. It is believed that embodiments described herein willbenefit other applications not specifically mentioned. Therefore, thespecific embodiments discussed are merely illustrative of specific waysto make and use the invention, and do not limit the scope of theinvention.

Shown in FIG. 1 a is a schematic cross-sectional diagram of thesemiconductor integrated circuit microelectronic device at an earlystage in its fabrication in accord with the preferred embodiments of theinvention. The intermediate device includes a substrate 101, which maycomprise Si, Ge, SiGe, GaAs, GaAlAs, InP, GaN, or combinations thereof.In addition to bulk wafers, the substrate 101 may also comprise siliconon insulator (SOI) technology. The substrate 101 preferably comprises ap-doped, (100) silicon wafer. The substrate 101 includes first 103 a andsecond 103 b active regions suitable for forming different semiconductordevices. Further included within the second active region 103 b is adoped well region 105, which is of opposite P or N polarity than thesubstrate 101 within the first active region 103 a.

An isolation structure, such as a shallow trench isolation (STI) region121, may be formed within the substrate 101 to isolate active regions.STI regions 121 are formed using conventional thermal growth methods andisolation region deposition and patterning methods. In FIG. 1, the firstactive region 103 a is laterally adjacent the second active region 103 bfor ease of illustration only and is not intended to limit embodimentsof the invention.

Formed over the active regions 103 is a gate dielectric layer 130. Thegate dielectric 130 may include a thermally grown silicon oxide having athickness from about 6 to 100 Å, and more preferably less than about 20Å. In other embodiments, the gate dielectric 130 may include a high-kdielectric having a k-value substantially greater than about 7. Possiblehigh-k dielectrics include Ta₂O₅, TiO₂, Al₂O₃, ZrO₂, HfO₂, Y₂O₃, L₂O₃,and their aluminates and silicates. Other suitable high-k gatedielectrics may include hafnium-based materials such as HfO₂, HfSiO_(x),HfAlO_(x).

A layer of gate electrode material 133 is formed over the gatedielectric 130 layer. The gate electrode material 133 may comprisemetals, metal alloys, metal-containing materials, polysilicon(polycrystalline silicon), and polycide (doped polysilicon/metalsilicide stack) gate electrode materials. Preferably, the gate electrodematerial 133 comprises chemical vapor deposition (CVD) polysiliconbetween about 100 and 10,000 angstroms thick and more preferably betweenabout 500 and 2,000 angstroms. The gate electrode material 133 mayfurther include about 1E20 cm-3 dopant of polarity opposite the channelregion of the corresponding MOS device to be formed therefrom. Suchdoping advantageously provides for enhanced off current (Ioff)performance, enhanced drain saturation current (Idsat) performance andpossibly enhanced short channel effect (SCE) performance of a fieldeffect transistor (FET) device formed employing a gate electrode formedfrom the patterned first gate electrode material layer 133.

FIG. 1 b illustrates an alternative embodiment of the invention whereinan optional glue layer 135 is formed between the dielectric layer 130and the gate electrode material 133. The glue layer 135 promotesadhesion between adjacent layers. It may be formed by CVD of polysilicon, amorphous silicon, TiN, Ti, Ta, TaN, or combinations thereof.

Turning now to FIG. 2 a, there is shown the intermediate structure ofFIG. 1 a after further processing according to embodiments of theinvention. A patterned masking layer 225 formed over the second activeregion 103 b, thereby leaving the first active region 103 a exposed. Themasking layer 225 may comprise a photo resist, an anti-reflectivecoating (ARC), a hard mask, or combinations thereof.

An amorphization implant, which is symbolized by arrows 230, isperformed next. The amorphization implant 230 may be a conventionalbeam-line ion implantation process, a plasma immersion ion implantation(PIII), or another ion implantation process known and used in the art.The implant 230 depth in the gate electrode material 133 is preferablyfrom about 100 to 5000 angstroms and more preferably from about 500 to1000 angstroms at a concentration of preferably from about 1E19 to 1E22atoms/cm2 and more preferably from about 1E20 to 1E21 atoms/cm2 usingIn, B, Sb, C, BF₂, or O atoms. Other preferred implant species mayinclude As, P, N, Ge, Ar, Kr, or combinations thereof.

As shown in FIG. 2 a, the amorphization implant 230 converts a portionof the gate electrode material over the first active region to anamorphous gate electrode material 133 a. Because the amorphizationimplant 230 does not fully penetrate the gate electrode material 133, aportion 133 b of the gate electrode material underlying the amorphousgate electrode material 133 a is unaffected by the amorphization implant230.

In an alternative embodiment of the invention shown in FIG. 2 b, theamorphization implant 230 implant fully penetrates the layer of gateelectrode material 133. Therefore, the gate electrode material over thefirst active region 103 a is essentially fully converted into a layer ofamorphous gate electrode material 133 a.

Turning now to FIG. 3 a, a capping layer 235 is formed over thestructure illustrated in FIG. 2 a. The capping layer 235 is preferablycomprised of a nitrogen-containing material such as silicon nitride,carbon doped silicon nitride, or more preferably silicon oxynitride(SiON). Suitable deposition methods include low pressure CVD (LPCVD),atomic layer deposition (ALD), PECVD, or RTCVD. By adjusting depositionparameters and precursor composition, the capping layer is preferablyformed as a low-stress film having an intrinsic stress <<10¹⁰ dyne/cm²,and more preferably ≈0 dyne/cm². The deposition temperature ispreferably below about 600° C. to avoid recrystallization of theamorphous gate electrode layer 133 a and more preferably between about350° C. and 550° C. The thickness of the capping layer 235 is preferablybetween about 100 and 1000 angstroms and more preferably between about200 and 500 angstroms.

As used herein, recrystallizing refers to the process that converts apolycrystalline material having a first grain size to a polycrystallinematerial having a second grain size. Recrystallizing may also refer tothe conversion of an amorphous material to a polycrystalline material.

Next, without removing the capping layer 235, an annealing process 245recrystallizes the gate electrode material as shown in FIG. 3 b. Theanneal 245 is preferably performed at about 600° C. to 1000° C. and morepreferably at about 700° C. to 950° C. using a rapid thermal anneal(RTA) or a spike anneal for at least about 3 seconds, or a furnaceanneal for about less than about 1 hr. The annealing process 245 mayfurther include an ambient atmosphere such as nitrogen.

As shown in FIG. 3 b, the annealing process 245 forms a first, second,and third recrystallized region, 133 c, 133 d, 133 e, of gate electrodematerial. The first recrystallized region 133 c is proportional in sizeto the pre-anneal amorphous region, which is symbolized by dashed linein FIG. 3 b. However, because crystal grain growth may have adirectional component, the first recrystallized region 133 c may belarger or smaller than the pre-anneal amorphous region. The secondrecrystallized region 133 d lies substantially under the firstcrystallized region 133 c. Together, the first and second recrystallizedregions, 133 c and 133 d, lie substantially over the first active region103 a of the substrate 101.

In preferred embodiments of the invention, the capping layer 235stabilizes the solid phase structure of the pre-anneal gate electrodematerial. That is, if the pre-anneal gate electrode is amorphous, thecapping layer 235 stabilizes the amorphous phase. If the pre-annealmaterial is polycrystalline, the capping layer 235 stabilizes thepolycrystalline phase. Therefore, during recrystallization, grain growthwithin the recrystallized gate electrode material, 133 c, 133 d and 133e, preferably proceeds from the gate oxide layer 130 towards the cappinglayer 235. Preferably, the third recrystallized region 133 e lies overthe second active region 103 b of the substrate, and it also liessubstantially adjacent the first and second recrystallized regions, 133c and 133 d.

In embodiments of the invention, a thickness, d1, of the firstrecrystallized region 133 c is preferably less than a thickness, d2, ofthe second recrystallized region 133 d. More preferably, d1 is betweenabout 0.5*d2 and 0.2*d2. In other embodiments of the invention, d1 isbetween about 200 and 450 A. In still other embodiments of theinvention, the first and second recrystallized regions, 133 c and 133 d,comprise nano-grain polysilicon. The nano-grain polysilicon may have acrystal grain size of about 10 nm or less in an embodiment of theinvention.

In other embodiments of the invention, d1 is approximately 0 nm. Such anembodiment corresponds to the situation where the amorphous region isinitially very thin and/or grain growth from the underlyingpolycrystalline region dominates the recrystallization. In yet stillother embodiments, d2 is approximately 0 nm. Such an arrangement maycorrespond to the further processing of the embodiment illustrated inFIG. 2 b, wherein the layer of gate electrode material over the firstactive region is fully converted to an amorphous layer (133 a, FIG. 2b).

Further details of the grain structure within the first, second, andthird recrystallized regions 133 c, 133 d, 133 e are illustrated in FIG.3 c. In a preferred embodiment of the invention, the thirdrecrystallized electrode material 133 e comprises a columnarpolycrystalline structure. The first and second recrystallized electrodematerials, 133 c and 133 d, may comprise a non-columnar polycrystallinegrain structure. More preferably, the first recrystallized region 133 ccomprises a first equiaxed grain structure 254, and the secondrecrystallized region 133 d comprises a second equiaxed grain structure256.

In the embodiment illustrated in FIG. 3 c, columnar grain boundaries 252are aligned substantially parallel with the growth axis of the substrate101. For example, if the substrate 101 has a (1,0,0) growth axis, thecolumnar growth axis may also be substantially aligned in a [1,0,0]direction, as shown in FIG. 3 c. In other embodiments (not shown), thecolumnar grain boundaries 252 may be inclined or even perpendicular tothe growth axis of the substrate 101.

In the embodiment illustrated in FIG. 3 c, the mean size of the firstequiaxed grains 254 is less than the mean size of the second equiaxedgrains 256, and the mean size of both of these grains is smaller thanthe mean size of the columnar grains 252. While the interfaces betweenthe plurality of recrystallized regions are illustrated as sharp,straight lines, one skilled in the art recognizes that this is for easeof illustration only. One so skilled understands that said interfacesmay be irregularly shaped and not clearly defined.

Yet another alternative preferred embodiment of the invention, the grainstructure of the recrystallized gate electrode material is schematicallyillustrated in FIG. 3 d. In this embodiment, the gate electrode materialis comprised of two regions, which may be labeled as a fourth 133 f anda fifth 133 g electrode material region. The grain structure of thefourth and fifth electrode material regions, 133 f and 133 g, isschematically represented by hexagons; however, amorphous materials arewithin the scope of embodiments of the invention. The fourth region 133f is formed over the first active region 103 a, and the fifth region 133g is formed over the second active region 103 b. In an embodiment, theforth and fifth regions, 133 f and 133 g, comprise recrystallizedregions, which may have a columnar or an equiaxed grain orientation, ora combination thereof. Preferably, an average grain size 262 within thefourth region 133 f is smaller than an average grain size 264 within thefifth region 133 g.

In an embodiment, the grain structure of the fourth region 133 fcomprises an amorphous material. This electrode material may be formedby processing the intermediate structure illustrated in FIG. 2 baccording to embodiments of the invention. In this embodiment, thecapping layer (see e.g., 235, FIG. 3 a) stabilizes the amorphous gateelectrode material (133 a, FIG. 2 b). The capping layer serves as anucleation barrier, thereby substantially limiting recrystallizationupon further processing. Therefore, the fourth electrode material 133 fin FIG. 3 d is recrystallized as described above, while the fifthelectrode material 133 g is amorphous.

As described above, other embodiments of the invention (not illustrated)may further include a glue layer (see e.g., 135 FIG. 1 b) interposedbetween the recrystallized gate electrode materials, 133 f and 133 g,and the gate dielectric 130. The glue layer advantageously promotesadhesion between the recrystallized gate electrode materials, 133 f and133 g, and the underlying gate dielectric 130.

Turning now to FIG. 4 a, there is illustrated a pair of gate electrodestacks formed after the further processing of the intermediate structureshown in FIG. 3 d. Formed over the first active region 103 a is a firstgate electrode stack 267 comprising a portion of the fourthrecrystallized gate electrode material 133 f that is patterned to form afirst polycrystalline gate electrode 269. Formed over the second activeregion 103 b is a second gate electrode stack 268 comprising a portionof the fifth recrystallized gate electrode material 133 g that ispatterned to form a second polycrystalline gate electrode 270.

The average grain size of the first gate electrode 269 is preferablysmaller than the average grain size of the second gate electrode 270.Preferably, the difference in the average grain size is greater thanabout 2 nm, and more preferably greater than about 10 nm. The graindistribution within the first and second gate electrodes, 269 and 270,may be widely distributed or mono-dispersed, randomly oriented, columnaror equiaxed, or combinations thereof.

In further keeping with embodiments of the invention, the respectivegrain size of each gate electrode induces a corresponding strain effectwithin an underlying substrate portion. Continuing with FIG. 4 a,underlying the first gate electrode stack 267 there is formed within thefirst active region 103 a first strain region 271. Underlying the secondgate electrode stack 268 there is formed within the second active region103 b a second strain region 273. Because the average grain size of thefirst gate electrode 269 is smaller than the average grain size of thesecond gate electrode 270, the first strain region 271 is advantageouslymore tensile (or less compressive) than the second strain region 273.Preferably, the first strain region 271 is tensile, and the secondstrain region 273 is compressive.

By allowing for the selective control of the gate electrode crystalgrains, embodiments of the invention provide methods and structures thatare optimized for the fabrication of NMOS and PMOS transistors. In theembodiment illustrated in FIG. 4 a, the preferred means of optimizationcomprises a difference in average crystal grain size. Other embodiments,as illustrated below, further enhance control of the strain within NMOSand PMOS regions.

Turning now to FIG. 4 b, there is illustrated a pair of gate electrodestacks formed after the further processing of the intermediate structureshown in FIG. 3 c. In the embodiment of FIG. 4 b, the first gateelectrode 269 preferably comprises a first and second sub-layer ofpatterned gate electrode material. In keeping with embodiments providedabove, the two layers comprise the first and second layers ofrecrystallized gate electrode material, 133 c and 133 d. The second gateelectrode 270 preferably comprises a patterned layer of the thirdrecrystallized gate electrode material 133 e. As described above, theaverage grain size of the first gate electrode 269 is preferably lessthan the second gate electrode 270.

As shown in FIG. 4 b, the first gate electrode 269 may comprise equiaxedgrains, and the second gate electrode may comprise columnar grains. Suchan arrangement of grains is preferred, but not required of embodimentsof the invention. For example, the first, second, and thirdrecrystallized layers of gate electrode material, 133 c, 133 d, 133 e,may independently comprise grains that are widely distributed ormono-dispersed, randomly oriented, columnar or equiaxed, or combinationsthereof. Most preferably, however, the average crystal grain size of thefirst gate electrode 269 is less than the average crystal grain size ofthe second gate electrode 270. In further keeping with embodiments ofthe invention provided above, the first strain region 271 is preferablymore tensile (less compressive) than the second strain region 273.

In order to further control the stress/strain distribution, embodimentsmay further include using implant dopants, which may induce or inhibitnucleation, grain growth, and recrystallization. Typically, a gateelectrode having an intrinsic compressive/tensile stress induces theopposite stress (i.e. tensile/compressive) within the substrateunderlying the gate electrode. For example, a gate electrode having anintrinsic tensile stress of about 4.50E9 dyne/cm² may induce acompressive stress in the channel region of approximately the samemagnitude. In other embodiments, a gate electrode having an intrinsictensile/compressive stress of about 2500 MPa may induce a correspondingchannel strain in the range of about compressive/tensile 1.5%.

Turning now to FIG. 5, the intermediate structures of FIGS. 4 a and 4 bmay be completed according to conventional semiconductor fabricationmethods, which may include several of the following steps. For example,completing the intermediate structure of FIG. 4 a may include forming aCMOS device comprising an NMOSFET 301 in the first active region 103 aand a PMOSFET 304 in the second active region 103 b. The capping layer(235, FIG. 4 a) is removed by etching using an acid such as HF, H₃ PO₄,or by using a dry etch.

Using the gate electrodes, 269 and 270, as a mask, lightly dopedsource/drain (LDS/LDD) regions are formed in the substrate 101 to adepth between about 100 and 1000 angstroms and preferably between about200 and 400 angstroms. An N-LDS/LDD region 307 is formed by ionimplanting phosphorus or arsenic dopant ions from about 1*10¹³ ions/cm2to about 5*10¹⁴ ions/cm² at an energy from about 30 keV to about 80 keV.After annealing the concentration of phosphorus or arsenic dopant in theLDS/LDD regions 307 is from about 5*10¹⁶ atoms/cm³ to about 1*10¹⁹atoms/cm³.

Between the N-LDS/LDD regions 307 there is an NMOS channel region 330.Preferably, the NMOS channel region 330 lies within the first strainregion 271. More preferably, the first strain region 271 comprises atensile stress that is aligned substantially between the N-LDS/LDDregions 307.

A P-LDS/LDD region 308 is formed by ion implanting boron or borondifluoride, BF₂, with a dose from about 1*10¹³ ions/cm² to about 5*10¹⁴ions/cm² at an energy from about 15 keV to about 50 keV. After annealingthe concentration of boron dopant in the P-LDS/LDD region 308 is about5*10¹⁶ atoms/cm³ to about 1*10¹⁹ atoms/cm³. Preferably, the PMOS channelregion 331 lies within the second strain region 273.

Formed on sidewalls of the gate electrodes 269 and 270 are sidewallspacers 315. The sidewall spacers 315 are a dielectric, such as CVDsilicon oxide. Using the gate electrodes 269 and 270 and also sidewallspacers 315 as a mask, heavily doped source/drain regions are formed.

Heavily doped P+ doped source/drain regions 319 in N-well 105 areself-aligned with gate electrode 270 and sidewall spacers 315. The P+source/drain regions 319 extend below the P− lightly doped LDS/LDDregions 308. The P+ regions source/drain regions may be implanted with adose of boron dopant in a range from about 1*10^(14 ions/cm) ² to about1*10¹⁶ ions/cm² at an energy from about 10 keV to about 80 keV. Afterannealing, the concentration of boron dopant in the regions 319 ispreferably between about 5*10¹⁸ atoms/cm³ and 5*10²⁰ atoms/cm³.

Heavily doped N+ doped source/drain regions 317 are formed in the firstactive area 103 a and self-aligned with gate electrode 269 and also withsidewall spacers 315. The heavily doped N+ source/drain regions 317preferably extend below the P− lightly doped LDS/LDD regions 307 asshown in FIG. 5. The heavily doped N+ source/drain 317 regions may beion implanted with a dose of phosphorus or arsenic dopant from about1*10^(14 ions/cm) ² to about 1*10^(16 ions/cm) ² at an energy from about10 keV to about 80 keV. After annealing, the concentration of phosphorusor arsenic dopant in the source/drain regions 317 is preferably betweenabout 5*10¹⁸ atoms/cm³ to about 5*10²⁰ atoms/cm³.

One skilled in the art will recognize that embodiments of the inventionmay be integrated with other methods and structures suitable forstrained channel transistors. For example, shallow trench isolation(STI) structures may induce stress in n-channel and p-channeltransistors separately. A first isolation trench may include a firstliner, and a second isolation trench may include a second liner. Theliners may comprise a suitable stress layer material, and it may be usedto modulate channel stress. For example, in modulating the channelstress may include implanting the liner with ions removed. A liner maybe modified in some but not all of a plurality of trenches.

For example, yet another embodiment of the invention may compriseincorporating a stressor 410 as shown in FIG. 6 a. The stressor 410 maycomprise a well-defined layer between the gate dielectric layer 130 andthe gate electrode 405. In such an embodiment, a thickness of thestressor 410 is preferably at least about 25% a thickness of the gateelectrode 405. In other embodiments, not illustrated, the stressor maynot be a distinct layer, but it may comprise a material dispersedthroughout of the gate electrode 405. As shown in FIG. 6 b, still otherembodiments may further include a glue layer 135 interposed between thestressor 410 and the gate dielectric 130.

Continuing with FIGS. 6 a and 6 b the stressor 410 may comprise amaterial having an intrinsic tensile or compressive stress. In otherembodiments, it may comprise a conductive material or a dielectric.Suitable compressive, conductive stressors 410 may comprise amorphoussilicon or SiGe. Suitable tensile, conductive stressors 410 may compriseNiSi, CoSi2, or poly Si. Suitable dielectric stressors 410, which aretensile or compressive depending on deposition method or stoichiometry,may comprise SiN, SiC, and/or oxides.

Another strained semiconductor method that may be integrated withembodiments includes forming a stressor such as a stress layer formedover NMOS and PMOS devices to induce a strain in the channel region. Forexample, a highly tensile stress/strain film is known to induce atensile channel stress/strain. Likewise, a highly compressivestress/strain film is known to induce a compressive channelstress/strain. Embodiments of the invention may further includedepositing a uniform stress film over a device, such as a CMOS deviceand thereafter modulating or adjusting an appropriate stress property ofthe film in order to achieve a desired channel stress.

One modulating treatment may comprise local stress relaxation by ionbombardment or implantation using, for example, germanium, silicon,xenon, argon, oxygen, nitrogen, carbon, or germanium, and combinationsthereof. Other treatments may include changing the composition (e.g.,oxidation and/or nitridation) of the stress layer using, for example, aprocess such as thermal, plasma, ozone, UV, a steam oxidation, a steamenvironment, and/or combinations thereof. Other treatment methods mayinclude film densification using, for example, a zone treatment, e-beamcuring, UV curing, laser treatment (either with or without an absorptionor reflection capping layer).

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, andcomposition of matter, means, methods and steps described in thespecification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

1. A semiconductor structure comprising: a first gate electrode over afirst active region, wherein the first gate electrode comprises one ofan amorphous gate electrode and a polycrystalline gate electrode; and apolycrystalline gate electrode over a second active region.
 2. Thesemiconductor structure of claim 1, wherein the first gate electrodecomprises an amorphous gate electrode, and the first active regioncomprises a tensile strained region under the amorphous gate electrode.3. The semiconductor structure of claim 2, wherein the second activeregion comprises a compressive strained region under the polycrystallinegate electrode.
 4. The semiconductor structure of claim 1, wherein thefirst gate electrode comprises an amorphous gate electrode, and thesecond gate electrode comprises a plurality of crystal grains having anequiaxed orientation.
 5. The semiconductor structure of claim 1, whereinthe first gate electrode comprises an amorphous gate electrode, and thesecond gate electrode comprises a plurality of crystal grains having acolumnar orientation.
 6. A semiconductor device comprising: a first gateelectrode over a first active region, the first gate electrodecomprising a first plurality of crystal grains having a first averagegrain size; and a second gate electrode over a second active region, thesecond gate electrode comprising a second plurality of crystal grainshaving a second average grain size, wherein the first average grain sizeis less than the second average grain size.
 7. The semiconductor deviceof claim 6, further comprising a tensile strain in the first activeregion and a compressive strain in the second active region.
 8. Thesemiconductor device of claim 7, further comprising a first stressorhaving an intrinsic compressive stress under the first gate electrode,and a second stressor having an intrinsic tensile stress under thesecond gate electrode.
 9. The semiconductor device of claim 8, wherein astressor thickness is at least about 25% of a gate electrode thickness.10. The semiconductor device of claim 6, wherein the first plurality ofcrystal grains comprises grains having one of columnar and equiaxedorientation and the second plurality of crystal grains comprises grainshaving the other of a columnar and an equiaxed orientation.
 11. Thesemiconductor device of claim 6, wherein the first and second pluralityof crystal grains independently comprise grains having a columnar or aequiaxed orientation.
 12. The semiconductor device of claim 6, whereinthe first plurality of crystal grains comprises grains having anequiaxed growth orientation.
 13. The semiconductor device of claim 12,wherein the first plurality of crystal grains comprises a first portionon a second portion, wherein an average crystal grain size of the firstportion is less than an average crystal grain size of the secondportion.
 14. The semiconductor device of claim 13, wherein the firstportion comprises crystal grains having one of a columnar and anequiaxed orientation and the second portion comprises the other ofcolumnar and equiaxed.
 15. The semiconductor device of claim 6, furthercomprising a gate dielectric layer under the first and second gateelectrodes, and a glue layer under the gate dielectric layer.
 16. Thesemiconductor device of claim 15, wherein the glue layer comprises amaterial selected from the group consisting essentially of poly silicon,amorphous silicon, TiN, Ti, Ta, TaN, and combinations thereof.
 17. Thesemiconductor device of claim 6, further comprising a gate dielectriclayer under the first and second gate electrodes, and a stressor overthe gate dielectric layer.
 18. The semiconductor device of claim 17,wherein the stressor comprises a material selected from the groupconsisting essentially of amorphous silicon, polysilicon, SiGe, NiSi,CoSi₂, SiN, SiC, an oxide, and combinations thereof.
 19. Thesemiconductor device of claim 6, wherein the first and second gateelectrodes comprise a material selected from the group consistingessentially of polysilicon, and a metal-containing material.
 20. Thesemiconductor device of claim 6, wherein the first gate electrodecomprises a material selected from the group consisting essentially ofAs, P, N, Ge, Ar, Kr, and combinations thereof.
 21. The semiconductordevice of claim 6, the wherein the first average grain size is at least2 nm less than the second average grain size.
 22. A semiconductor devicecomprising: an NMOS device and a PMOS device, each device comprising asource/drain region in a substrate, a channel region in the substratebetween the source/drain region, and a polycrystalline gate electrodeover the channel region; wherein an average crystal grain size of theNMOS polycrystalline gate electrode is smaller than an average crystalgrain size of the PMOS polycrystalline gate electrode.
 23. Thesemiconductor device of claim 22, wherein the NMOS polycrystalline gateelectrode comprises a material having an intrinsic compressive stress.24. The semiconductor device of claim 23, wherein the NMOSpolycrystalline gate electrode causes a tensile strain in the NMOSchannel region.
 25. The semiconductor device of claim 22, wherein thePMOS polycrystalline gate electrode comprises a material having anintrinsic tensile stress.
 26. The semiconductor device of claim 25,wherein the PMOS polycrystalline gate electrode causes a compressivestrain in the PMOS channel region.
 27. The semiconductor device of claim22, wherein the NMOS and the PMOS polycrystalline gate electrodeindependently comprise a material selected from the group consistingessentially of silicon, germanium, and combinations thereof.